1. Technical Field
The present invention relates to a method and device operable to determine a duty cycle offset of a periodic signal. More specifically, the present invention relates to a method and device operable to determine a duty cycle offset of a periodic signal and correct the periodic signal to a desired duty cycle.
2. Description of the Related Art
The “duty cycle” of a periodic signal is the fraction of the time the periodic signal is at logic ‘1’ over the period of the periodic signal. Thus, if a periodic signal is at logic ‘1’ for 100 picoseconds and has a period of 400 picoseconds, the periodic signal has a duty cycle of 25%. If the periodic signal had a period of 200 picoseconds and the periodic signal is at logic ‘1’ for 100 picoseconds, the duty cycle is 50%. When the duty cycle is 50%, the periodic signal is at logic ‘1’ for the same length of time it is at logic ‘0’. The periodic signal may be a clock signal. In such a case, the period of the clock signal may also be referred to as a “clock cycle”. The term “clock high” refers to when a clock signal is at logic ‘1’. The term “clock low” refers to when a clock signal is at logic ‘0’.
Keeping a 50% duty cycle for the main clock in a processor (and for other high frequency clocks in the processor) is one of the most potent ways of increasing the clock frequency for the processor and decreasing the impact of phase paths within the processor. A “phase path” occurs when a signal does not have an entire clock period to propagate. For example, a signal may be clocked out of a first flip flop on a rising edge of a clock and need to propagate to a second flip flop to be clocked in on a falling edge of the clock. Thus, if the clock period is 250 picoseconds and the signal requires at least 100 picoseconds to propagate, then a duty cycle of less than 40% will severely impact this phase path.
When the duty cycle of a clock is not equal to a desired duty cycle, the duty cycle is said to have an “offset”. The desired duty cycle is typically 50%. The offset is an amount of time the logic ‘1’ portion of the clock is above or below the amount of time necessary for the desired duty cycle. If the desired duty cycle is 50%, for a clock having a period of 200 picoseconds, 50% duty cycle is logic ‘1’ for 100 picoseconds. If the duty cycle is actually 40%, the offset is −20 picoseconds (i.e., the logic ‘1’ portion of the clock is only 80 picoseconds). If the duty cycle is actually 55%, the offset is +10 picoseconds. An offset may also be referred to as an “excursion”.
Significant duty cycle offsets for the main processor clock were observed by the silicon debug teams for the Intel Merom and Penryn chipsets. It has been proven by the silicon debug teams for both the Merom and Penryn chipsets that tuning the duty cycle of the processor clock closer to 50% enhances the performance of the chip. Currently this is accomplished using fuses which store control information for a chain of inverting elements having controllable P/N ratios. The deficiency of this method is that each individual chip requires a different fuse setting due to the variability and unpredictability of the process.
Measuring the duty cycle of each individual chip in a production environment is difficult and expensive. Furthermore, burning different fuse content based on these measurements is also expensive.
Directly measuring the time difference between the logic ‘1’ portion and the logic ‘0’ portion of a clock is quite difficult. One problem with measuring a clock's duty cycle is the need to measure incredibly small amounts of time using very imprecise elements that have coarse resolution. For example, transistor properties are impacted by process variation, within die variation, voltage variation, etc.
Until now, the measurement of the duty cycle was performed only with instruments external to the chip. For example, a production tester may test a processor over a range of frequencies (such a process is referred to as “frequency shmoo”). No solution exists for detecting a duty cycle internal to the chip. Furthermore, no solution exists for detecting a duty cycle which is workable on silicon.